The present invention relates to circuits for interfacing a first type of logic circuit with a second type of logic circuit and, more particularly, to circuits for interfacing such logic circuits wherein the first type of logic circuit has a larger output logic level swing as compared to the input logic level swing of the second type of logic circuit.
It is known that III-V compound MESFET (metal semiconductor field effect transistor) circuits such as GaAs (gallium arsenide) MESFET logic circuits are widely used for high-speed applications such as optical data connections having a data rate up to several tens of Gigahertz. The optical data links are used for data communication in distributed computer systems or clustered systems as system area networks.
From the system point of view, the controls to the GaAs MESFET logic circuit are coming from the system (e.g., distributed computer system or clustered system), which is usually built with silicon-based CMOS (complementary metal oxide semiconductor) logic. Thus, silicon CMOS logic to MESFET logic interface circuitry is typically necessary.
FIG. 1 shows the logic family of MESFET logic gates: (a) buffered field effect transistor logic (BFL); (b) field effect transistor logic (FL); (c) Schottky diode field effect transistor logic (SDFL); (d) feed forward field effect transistor logic (FFFL); (e) capacitor diode field effect transistor logic (CDFL); (f) capacitor coupled field effect transistor logic (CCFL); and (g) source coupled field effect transistor logic (SCFL). The gate-source junction of a MESFET is a forward biased diode when a positive voltage is applied at the gate to turn the transistor on. Since the input of the MESFET logic is directly to the gate of a MESFET as shown in FIG. 1, the input swing should be limited from GND to 0.7V. Otherwise, the input voltage will forward-bias the gate-source diode resulting in a very large gate-source current such as several milliamps (mA) to several tens of milliamps, depending on the design, due to the exponential characteristic of current versus voltage as shown in FIG. 2. In order to apply a rail-to-rail CMOS logic output to the MESFET logic, the CMOS logic "high" should be reduced or clamped less than 0.6V, but higher than the threshold voltage of the MESFET, which is for example 0.2V.
FIG. 3(a) and (b) illustrate examples of conventional CMOS to MESFET logic interface circuits. These conventional interface circuits use several fixed diode on-voltage drops (denoted as n), and are only good for a fixed supply voltage. In system applications, typically .+-.10% of the supply voltage margin should be allowed. If the supply voltage is 5 volt (V), the margin in the supply voltage is .+-.0.5V yielding a total difference of 1V, which is even more than one diode voltage drop. So, the voltage drop through the fixed number of diodes can easily exceed the diode on-voltage and, again, due to the exponential characteristics of current versus voltage as shown in FIG. 2, the current is very large and results in high power consumption.
U.S. Pat. No. 5,286,985 to Taddiken discloses an interface circuit for connecting GaAs circuits with silicon circuits using a mix of GaAs and silicon devices. An exemplary illustration of such an approach is shown in FIG. 4(a) where CMOS logic circuit A is interfaced to MESFET logic circuit C via mixed technology interface circuit B. However, this approach is applicable only to GaAs and CMOS mixed technology because the interface circuit, itself, includes both CMOS devices and MESFET devices. Even if this interface circuit were designed in separated CMOS and GaAs technologies, as illustrated in FIG. 4(b), the CMOS logic circuit A, which is an open-drain output, would still require that the CMOS transistor 10 be in the interface circuit B, as denoted by the phantom box in FIG. 4(b). Hence, this interface circuit would be useful only if the CMOS open-drain output circuit A was specifically designed to use this interface circuit. However, as completed CMOS systems do not usually support open-drain output, the Taddiken interface circuit is not applicable for most cases.
Accordingly, it would be highly advantageous to provide a circuit for interfacing a first type of logic circuit with a second type of logic circuit wherein the interface circuit is composed of only logic devices of the second type capable of receiving typical output signals from logic devices of the first type. Such an inventive interface circuit would enable the easy separation of the two types of circuit technology.